VLSI Training Institute
Verilog RTL Design Flow with FPGA Entry Level

This course covers the Verilog RTL syntax and implementing the Industry standard RTL logic. The written logic is validated using Functional simulation as well as checking the behaviour by programming into standard FPGA platform

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Verilog RTL Design Flow with FPGA for Entry Level

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Embedded Systems Training

This course covers the Verilog RTL syntax and implementing the Industry standard RTL logic. The written logic is validated using Functional simulation as well as checking the behaviour by programming into standard FPGA platform

Course Details

Logic Byte offers 12-week Program for students recently completed their graduation, with B.E/B.Tech, M.E./M.Tech in Electronics & communication. This program is specifically designed with an objective to spark an interest in core electronics, specifically in the VHDL domain with industry level complexity. The program provides insight into fundamentals of the concepts necessary to build a strong foundation & hands on experience on RTL usage. This course covers the basics of RTL design, basics of FPGA and RTL design Target to FPGA, functional simulation and programming to fpga and fpga debug using available tools. The participants will get an opportunity to work on projects during the course.

Requirements

  • Graduation or post graduation in Electronics and communication or equivalent discipline
  • Basic understanding on digital logic
  • Basic understanding on digital electronics
  • Basic knowledge on hardware description language
  • Candidates must clear the online test before

Eligibility Criteria

  • Graduate in Electronics & Communication Engineering(BE/B.Tech) who is looking to start their careers in VLSI Engineer.
  • Post-Graduate (M.Tech, PhD, M.Sc) with specializations like VLSI, Instrumentation and Embedded Systems etc. who have graduated recently.
  • Experienced graduates/post-graduates with the above mentioned qualifications who wish to change into the VLSI domain.

Certification

On course completion Successful Candidate will be issued a Digital Certificate. Which can also be verified online by scanning QR code, which is shared on Successful completion of course.

Introduction to Digital Electronics 2 Days Download
Digital Design Concepts 2 Days Download
Digital logics 2 Days Download
Introduction to HDL & Verilog Concepts 3 Days Download
Writing codes to basic digital logics 3 Days Download
Introduction to Vivado, Functional Simulation & Test Benches 2 Days Download
Optional: Working with Modelsim (Quartus) 2 Days Download
Simulate the previously written Verilog codes 2 Days Download
RTL design and Functional Simulation Using Vivado 4 Days Download
Documentation 2 Days Download
Introduction to FPGA and Introduction to synthesis, P & R, Bit stream generation & Hands On 5 Days Download
Programming FPGA and Debugging design using JTAG 1 Days Download
Complete RTL Design, Compilation & FPGA programming Hands on 4 Days Download
AXI Interface 2 Days Download
Introduction to Communication Protocol 2 Days Download
Examples to implement simple protocols in FPGA 2 Days Download
Comparison between FPGA Design and ASIC Design 2 Days Download
Hands on RTL Design and FPGA programming 6 Days Download
Working On current Industry standard projects 21days Download
Resume Preparations & Mock Interview 3days
teacher

Neha Kumari   ||   RTL Designer

Neha is having vast working experience on:
• Expertise in RTL logic design, simulation and FPGA/CPLD design flow & verification.
• Hands on experience on Xilinx devices, Xilinx tools and high-speed IP cores.
• Development of test plan and setup the test bench in VHDL and test environment.
• Debugging of Hardware board.
• Resolved client technical problems utilizing digital and analytical skills.

Skills:
• Hardware Descriptive Language : VHDL, Verilog HDL.
• Hardware : FPGA (Zed Board), Spartan- 3E, Spartan6, Arduino.
• Programming Language : MATLAB, C, Basics of Embedded C and basics of C++, Data structure, Assembly level language of 8085 and 8051.
• Scripting language : Shell Script, Basics of PERL, Basics of TCL.
• Tools Used : Vivado, Xilinx ISE / EDK, Modelsim, LTspice.
• Debugging : Xlinix Chipscope logic analyzer, High speed Oscilloscope.
• Office tools : Advance Excel, Ms word, Ms power point.
• Operating System : win7, win10, UBUNTU (Linux), UNIX.

teacher

Saravana   ||   Digital Circuits

Sarvana is having vast working experience on :
• Design and development of various HDL modules using Xilinx Spartan-3E FPGA board.
• Xilinx FPGA board programming using ISE.
• Design HDL modules using Xilinx IP cores.
• Designing Projects using Schematic Entry in Xilinx Simulator.
• Design logic level and physical layout verification using Microwind.
• Experienced in VHDL, Verilog, Xilinx Spartan FPGA programming.
• Expertise in Digital Design
• Proficient in RTL design, simulation and synthesis using Xilinx ISE, XST tools.
• Experienced with Xilinx EDK Platform.
• Knowledgeable in CMOS VLSI design, Verilog RTL coding.
JOURNALS: • Publication of the journal in International Journal of Advances in Engineering & Technology under the topic of “Area Minimization of Carry Select Adder using Boolean algebra”

teacher

Rajesh Joshi   ||   FPGA

Rajesh Joshi is experienced with FPGA DSP. He is having vast working experience on ANALOG AND DIGITAL COMMUNICATION, SIGNALS AND SYSTEM, DIGITAL ELECTRONICS, WIRELESS COMMUNICATION, AUTOMATIC,CONTROL SYSTEM, DIGITAL SIGNAL PROCESSING. He has achieved physical application of AM-SSB, FM, AM-DSB, Digital AGC and Squelch (Module), DUC(Digital Up Converter) and DDC (Digital Down Converter), Adaptive Linear Equalizer based on LMS Technique, Low Data Rate waveform (up to 64 Kbps), High Data Rate Waveform ( up to 2 & 6 Mbps), Phase Offset and frequency Offset/Doppler Correction Techniques, Symbol Timing Recovery, Phase Ambiguity Resolution for PSK Modulated Signals, SNR Estimation Method for TCC Decoder.

client

Rajesh Joshi

Good Knowledge on All Concepts

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