Faculty

Saravana

Sarvana is having vast working experience on :
• Design and development of various HDL modules using Xilinx Spartan-3E FPGA board.
• Xilinx FPGA board programming using ISE.
• Design HDL modules using Xilinx IP cores.
• Designing Projects using Schematic Entry in Xilinx Simulator.
• Design logic level and physical layout verification using Microwind.
• Experienced in VHDL, Verilog, Xilinx Spartan FPGA programming.
• Expertise in Digital Design
• Proficient in RTL design, simulation and synthesis using Xilinx ISE, XST tools.
• Experienced with Xilinx EDK Platform.
• Knowledgeable in CMOS VLSI design, Verilog RTL coding.
JOURNALS: • Publication of the journal in International Journal of Advances in Engineering & Technology under the topic of "Area Minimization of Carry Select Adder using Boolean algebra"

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Rajesh Joshi

Rajesh Joshi is experienced with FPGA DSP. He is having vast working experience on ANALOG AND DIGITAL COMMUNICATION, SIGNALS AND SYSTEM, DIGITAL ELECTRONICS, WIRELESS COMMUNICATION, AUTOMATIC,CONTROL SYSTEM, DIGITAL SIGNAL PROCESSING. He has achieved physical application of AM-SSB, FM, AM-DSB, Digital AGC and Squelch (Module), DUC(Digital Up Converter) and DDC (Digital Down Converter), Adaptive Linear Equalizer based on LMS Technique, Low Data Rate waveform (up to 64 Kbps), High Data Rate Waveform ( up to 2 & 6 Mbps), Phase Offset and frequency Offset/Doppler Correction Techniques, Symbol Timing Recovery, Phase Ambiguity Resolution for PSK Modulated Signals, SNR Estimation Method for TCC Decoder.

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