program

Sl.# Course Code Batch No Course Name Choose Date Location Duration Status Registration
1 ELRTL-1219 HDL-RTL-121901 Verilog RTL Design Flow with FPGA Entry Level 02 Dec 2019 Rajarajeshwari Nagar, Bengaluru 12 Weeks Open Registration
Sl.# Course Code Batch No Course Name Choose Date Location Duration Status Registration
1 HWSDF-001 HWSDF-121901 Schematics design flow and board bring up 01 Jan 1970 Rajarajeshwari Nagar, Bengaluru 12 Weeks Open Registration
Sl.# Course Code Batch No Course Name Choose Date Location Duration Status Registration
1 AP-001 AP-121901 Short Term Project 16 Jan 2020 Rajarajeshwari Nagar, Bengaluru 12 Weeks Open Registration