Training Calender

Sl # Courses Code Courses Start Date Training Location Duration Register
1 ELRTL-1219 Verilog RTL Design Flow with FPGA Entry Level 02 Dec 2019 Rajarajeshwari Nagar, Bengaluru 12 Weeks Register
2 HWSDF-001 Schematics design flow and board bring up Tentative Date
16 Jan 2020
Rajarajeshwari Nagar, Bengaluru 12 Weeks Register
3 AP-001 Short Term Project 16 Jan 2020 Rajarajeshwari Nagar, Bengaluru 12 Weeks Register